Display technologies are an example where the structural incompatibilities in conjunction with the low thermal budget of most transparent substrates (typically glass or plastic substrates) inhibit the formation on the substrate of single-crystalline semiconductors which are required to integrate high performance semiconducting devices with differing functionality. Examples of such devices include npn transistors and pnp transistors (e.g. to form Complementary Metal Oxide Semiconductor (CMOS) circuits), pressure sensors (e.g. for haptic interfaces), light sensors (e.g. for adapting the display to the ambient lighting conditions) and last but not least red, green and blue Light Emitting Devices (LEDs) (e.g. for emissive displays) on transparent substrates which may also be flexible.
These devices may contain elongate low dimensional structures, which are formed onto a suitable substrate (a “formation substrate”) but can be subsequently transferred onto a different substrate (known as a “target substrate” or “receiver substrate”). Examples of devices which may contain elongate low dimensional structures include but are not restricted to npn transistors, pnp transistors, sensors, capacitors, red, green and blue LEDs. The bulk of the receiver substrate may consist of glass, polymers, metals, or semiconductors or any combination of these materials. Forming the devices on a formation substrate and transferring them to a receiver substrate overcomes any incompatibility between the formation process and the receiver and/or earlier formed devices.
Where physically different structures consisting of or containing low dimensional structures are formed on a formation substrate and are transferred to a target substrate, it is often desirable to be able to exercise a degree of control over the arrangement of these devices on the target substrate, both with respect to predefined features on the target substrate and with respect to each other.
Additionally, stacking device layers enables higher device densities and increased interconnectivity. This is of particular advantage for displays used in mobile devices (e.g. mobile phones, PA's), requiring a stringent form-factor.
The term “low dimensional structure” as used herein refers to a structure that has at least one dimension that is much less than at least a second dimension.
The term “elongate structure” as used herein refers to a structure having two dimensions that are much less than a third dimension. The definition of an “elongate structure” lies within the definition of a “low dimensional structure”, and a nanowire is an example of a structure that is both a low dimensional structure and an elongate structure.
Low dimensional structures that are not elongate structures are known. For example, a ‘platelet’, which has two dimensions of comparable magnitude to one another and a third (thickness) dimension that is much less than the first two dimensions constitutes a “low dimensional structure” but is not an “elongate structure”.
For the avoidance of any doubt, the term “physically different” means in the context of this invention that those sections of the elongate low dimensional structure which determine the device performance differ in at least one of the following points:                1. material composition        2. material composition profile        3. cross-sectional geometry (e.g. different side facets at different sections along the low dimensional elongate structures)        4. cross sectional area        5. crystallographic orientation        6. length        
Methods are known for transferring devices from a first substrate to a second substrate. However, at present no suitable techniques are available for applying a high density of devices to a receiver substrate such that all of the following desiderata are met:                1. More than two device layers can be integrated onto a receiver substrate.        2. The achievable number of inter-layer interconnects can be greater than the lowest number of devices contained in a device layer.        3. The inter-layer device interconnects do not increase the footprint of the corresponding circuits considerably.        4. The way the inter-layer device interconnects are formed and the way the devices are arranged within each layer does not impose constraints onto the type of circuit architecture to be realized (e.g. no limitation to cross-bar architectures) allowing to combine different architectures.        5. The vias of the inter-layer device interconnects can be defined using conventional lithography.        6. No thinning of the transferred structures before or after the transfer is required.        7. No Silicon-on-Insulator (SOI) material is required.        
A. W. Topol et al. give, in IBM Journal of Research & Development, Volume 50, Number 4/5, p 491 (2006), an overview of achieving three-dimensional integrated circuits by wafer bonding techniques. Face-to-face bonding is limited to a maximum of two device layers, while face-to-back bonding suffers from a low interlayer via density. This problem can be mitigated by using a SOI-based face-to-back bonding process, but this is more costly.
Science Vol. 314, p. 1754 (2006) demonstrated the assembly of device layers of physically different devices on a polymer substrate. Each device layer is separated by a polymer layer. Vias are formed by a combination of photolithography and etch techniques.
Nano Letters Vol. 7, No. 3, p. 773 (2007) demonstrates the assembly of different layers of nanowire devices using a dry transfer method. No interlayer device interconnects are formed and no information is provided how inter-layer device interconnects could be formed. Furthermore, the nanowires show poor edge alignment, imposing a challenge on forming interconnects between particular sections of nanowires belonging to different device layers.
U.S. Pat. No. 6,920,260 and U.S. Pat. No. 7,073,157 describe array-based architectures for molecular electronics. The array consists of conducting electrodes which cross each other. In between these electrodes a molecular junction is formed. The electrodes could be implemented by using two layers of aligned nanowires with the nanowires of the first layer being aligned perpendicular to the nanowires of the second layer.
Nano-Networks and Workshops, 2006, NanoNet '06. 1st International Conference on, pp. 1-5 (ISBN: 1-4244-0391-X) describes a 3D nanowire-based programmable logic architecture based on a cross-bar arrangement. This publication, as well as U.S. Ser. No. 06/920,260 and U.S. Pat. No. 7,073,157B2, describe architectures which are confined to a cross-bar arrangement.
U.S. Pat. No. 7,193,239 describes three-dimensional semiconductor circuits formed by stacking substrates having monolithically integrated circuits. The topside of a circuit layer is bonded to a substrate, and the exposed backside of the substrate is thinned to 50 mm or less. Feed-throughs are then formed in registration with contacts of the circuit layer. The steps of bonding, thinning, and forming feed-throughs are then repeated for subsequent circuit layers.
Co-pending UK patent application GB2442768 describes a method of making encapsulated low dimensional structures such that they are suitable to be transferred to a different substrate. During the transfer the number of elongate structures, their alignment, spacing, and their orientation are maintained. Furthermore, these structures can be subsequently processed into devices using conventional lithographic methods in combination with subtractive (e.g. dry etching) and additive techniques (e.g. metal deposition).
The current invention addresses the challenge of providing an improved method of fabricating three dimensional device architectures on a receiver substrate. Preferably, the method would allow most or all of the following desiderata to be met:                1. More than two device layers can be integrated onto a receiver substrate.        2. The achievable number of inter-layer interconnects can be greater than the lowest number of devices contained in a device layer.        3. The inter-layer device interconnects do not increase the footprint of the corresponding circuits considerably.        4. The way the inter-layer device interconnects are formed and the way the devices are arranged within each layer does not impose constraints onto the type of circuit architecture to be realized (e.g. no limitation to cross-bar architectures) allowing to combine different architectures.        5. The vias of the inter-layer device interconnects can be defined using conventional lithography.        6. No thinning of the transferred structures before or after the transfer is required.        7. No Silicon-on-Insulator material is required.        8. Different device layers may contain physically different devices.        